1. Field of the Invention
This invention relates to semiconductor memories and more particularly to EPROM cells and the method of manufacture thereof.
2. Description of Related Art
FIG. 2 shows a conventional prior art Flash EPROM cell 10 formed starting with a P-substrate 11 including N+ source region 16, N+ drain region 17 and N- region 18. Doped regions 18 and 17 define the ends of the channel region 19. Directly above the channel region 19 and above tunnel oxide layer 12 is formed a three level stack including from bottom to top (polysilicon 1) floating gate 13, (ONO) interpolysilicon dielectric 14 and (polysilicon 2) control gate 15. The floating gate 13 is formed on the tunnel oxide layer 12. Interpolysilicon dielectric layer 14 overlies the floating gate 13. Control gate 15 overlies the interpolysilicon dielectric layer 14. The lower left edge of floating gate 13 overlies the right end of N+ region 16 in the substrate 11. The lower right edge of floating gate 13 overlies the left end of N+ region 17 in substrate 11. Beneath the N+ source region 16 is the N- region 18 which extends a short distance beneath tunnel oxide layer 12 under the left end of floating gate 13. A significant drawback of this design is that a dual power supply is needed. To program the memory cell shown in FIG. 2, the drain voltage required is about 7 Volts. As an example of the programming condition the parameters are as follows:
V.sub.D =7 Volts Drain
V.sub.CG =12 Volts Control Gate
V.sub.S =0 Volts Source
The above voltages are required to have a field sufficient for hot channel electrons for injection from the drain Junction into the floating gate.